1. Design of high-performance quaternary half adder, full adder, and multiplier

Analog Integrated Circuits and Signal Processing, Springer, 2025

2. Simultaneous power, delay, and crosstalk noise reduction for the BUS encoding method of ternary LWC plus quaternary TS

International Journal of Electronics, Taylor and Francis, 2025

3. Design of new low-power and high-speed quaternary flip-flops based on CNTFETs

Computers and Electrical Engineering, Elsevier, 2024

4. DAFA: Dynamic approximate full adders for high area and energy efficiency

Integration, Elsevier, 2024

5. 21T ternary full adder based on capacitive threshold logic and carbon nanotube FETs

IEEE Transactions on Nanotechnology, IEEE, 2024

6. Low-power bus encoding by ternary LWC and quaternary transition signaling: From initial concept to circuit design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2024

7. Design and evaluation of ultra‐fast 8‐bit approximate multipliers using novel multicolumn inexact compressors

International Journal of Circuit Theory and Applications, Wiley, 2023

8. Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

IET Circuits, Devices & Systems, IET, 2023

9. Design and Implementation of a High-Speed and Low-Energy Approximate Full Adder Cell with CNFET Technology Applicable in Image Processing

Tabriz Journal of Electrical Engineering, 2023

10. How Alligator-Clip Compounds Affect The IV Characteristic of Molecular Devices, A DFT Approach

Iranian Journal of Applied Physics, 2022

11. Systematic transistor sizing of a CNFET-based ternary inverter for high performance and noise margin enlargement

IEEE Access, IEEE, 2022

12. Towards effective offloading mechanisms in fog computing

Multimedia Tools and Applications, Springer, 2022

13. Design and simulation of reliable and fast nanomagnetic conservative quantum-dot cellular automata (NCQCA) gate

Journal of Computational Electronics, Springer, 2021

14. High-performance quaternary latch and D-type flip-flop with selective outputs

Microelectronics Journal, Elsevier, 2021

15. Two novel current-mode CNFET-based full adders using ULPD as voltage regulator

Journal of Circuits, Systems and Computers, World Scientific, 2021

16. Utilization of binary circuits for an edge-triggered quaternary D flip-flop by carbon nanotube FETs

26th International CSI Computer Conference, 2021

17. Design and evaluation of a carry-skip adder in quantum cellular automata technology

Tabriz Journal of Electrical Engineering, 2021

18. Triangular quantum-dot cellular automata wire for standard ternary logic

International Journal of Theoretical Physics, Springer, 2020

19. Ternary limited-weight codes and quaternary transition-signaling for low-power bus encoding

IEEE 14th Dallas Circuits and Systems Conference, 2020

20. Noise margin calculation in multiple-valued logic

10th International Conference on Computer and Knowledge Engineering, 2020

21. High-performance CML approximate full adders for image processing application of Laplace transform

Circuit World, Emerald, 2020

22. A universal method for designing multi-digit ternary to binary converter using CNTFET

Journal of Circuits, Systems and Computers, World Scientific, 2020

23. Novel implementation of 3D multiplexers in nano magnetic logic technology

Microelectronics International, Emerald, 2020

24. CMOS arbiter physical unclonable function with selecting modules

20th International Symposium on Computer Architecture and Digital Systems, 2020

25. Multi valued parity generator based on Sudoku tables: Properties and detection probability

IET Communications, IET, 2020

26. Partial ternary full adder versus complete ternary full adder

International Conference on Electrical, Communication, and Computer Engineering, 2020

27. Ternary DDCVSL: A combined dynamic logic style for standard ternary logic with single power source

IET Computers & Digital Techniques, IET, 2020

28. Design and evaluation of clocked nanomagnetic logic conservative Fredkin gate

Journal of Computational Electronics, Springer, 2020

29. Ternary DCVS half adder with built-in boosters

Journal of Intelligent Procedures in Electrical Technology, 2020

30. Analytical review of noise margin in MVL: Clarification of a deceptive matter

Circuits, Systems, and Signal Processing, Springer, 2019

31. A novel 3D three/five-input majority-based full adder in nanomagnetic logic

Journal of Computational Electronics, Springer, 2019

32. MIPS-Core Application Specific Instruction-Set Processor for IDEA Cryptography-Comparison between Single-Cycle and Multi-Cycle Architectures

arXiv preprint arXiv:1903.00191, 2019

33. Applicability of Partial Ternary Full Adder in Ternary Arithmetic Units

arXiv preprint arXiv:1902.06742, 2019

34. Ab initio study of spin polarization and Acetylene transition distance effects on structural and transconductance properties of molecular Tour wires

2nd International Conference on Applied Research in Mathematical Sciences and Physics, 2019

35. Partial product generation for unbalanced ternary signed multiplication

International Journal of High Performance Systems Architecture, Inderscience, 2019

36. On the design methodology of Boolean functions with quantum-dot cellular automata for reducing delay and number of wire crossings

Journal of Computational Electronics, Springer, 2018

37. Effective realization of ternary logic circuits by adapted map minimization method

8th International Conference on Computer and Knowledge Engineering, 2018

38. A capacitive multi-threshold threshold gate design to reach a high-performance PVT-tolerant 4:2 compressor by carbon nanotube FETs

Analog Integrated Circuits and Signal Processing, Springer, 2018

39. Review of Ternary Half Adders with Decoded Input Signals

4th International Conference on Knowledge-Based Engineering and Innovation, 2017

40. High-performance ternary (4:2) compressor based on capacitive threshold logic

International Journal of Electronics and Telecommunications, 2017

41. High-performance ternary operators for scrambling

Integration, Elsevier, 2017

42. Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5

Engineering Science and Technology, an International Journal, Elsevier, 2017

43. A single parity-check digit for one trit error detection in ternary communication systems: Gate-level and transistor-level designs

Journal of Multiple-Valued Logic & Soft Computing, Old City Publishing, 2017

44. Physical unclonable functions based on carbon nanotube FETs

IEEE 47th International Symposium on Multiple-Valued Logic, 2017

45. A novel high-speed, low-power CNTFET-based inexact full adder cell for image processing application of motion detector

Journal of Circuits, Systems and Computers, World Scientific, 2017

46. Non-preemptive offline multi-job mapping for a photonic network on a chip

Nano Communication Networks, Elsevier, 2017

47. Design of a ternary edge-sensitive D FFF for multiple-valued sequential logic

Journal of Low Power Electronics, ASP, 2017

48. A new algorithm for constructing the 2nd phase of multiplier by using full compressors, targeting hardware efficiency and reduction of half adders

22nd National CSI Computer Conference, 2017

49. Design of a ternary half adder cell by using capacitive summation in DCVSL

22nd National CSI Computer Conference, 2017

50. Comparison of QCA 4×1 Multiplexer Designs

The First National Conference on Nanotechnology, 2017

51. Integration of CTL, PTL, and DCVSL for designing a novel fast ternary half adder

The CSI Journal on Computer Science and Engineering, 2017

52. Multiplication With m:2 and m:3 Compressors—A Comparative Review

Canadian Journal of Electrical and Computer Engineering, IEEE, 2017

53. A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates

IET Circuits, Devices & Systems, IET, 2017

54. Robust fuzzy SRAM for accurate and ultra‐low‐power MVL and fuzzy logic applications

Electronics Letters, IET, 2016

55. Ternary cyclic redundancy check by a new hardware-friendly ternary operator

Microelectronics Journal, Elsevier, 2016

56. On the design of fully symmetrical bridge-style circuits

IETE Journal of Research, Taylor and Francis, 2016

57. Ternary versus binary multiplication with current-mode CNTFET-based K-valued converters

IEEE 46th International Symposium on Multiple-Valued Logic, 2016

58. A new hybrid 16-bit x 16-bit multiplier architecture by m:2 and m:3 compressors

International Journal of Information and Electronics Engineering, 2016

59. New current-mode multipliers by CNTFET-based n-valued binary converters

IEICE Transactions on Electronics, IEICE, 2016

60. From static ternary adders to high‐performance race‐free dynamic ones

The Journal of Engineering, IET, 2015

61. Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple‐valued logic and fuzzy logic

IET Circuits, Devices & Systems, IET, 2015

62. A novel low-energy CNFET-based full adder cell using pass-transistor logic

International Journal of High Performance Systems Architecture, Inderscience, 2015

63. New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources

International Journal of High Performance Systems Architecture, Inderscience, 2015

64. New current-mode integrated ternary min/max circuits without constant independent current sources

Journal of Electrical and Computer Engineering, Hindawi, 2015

65. Optimized adder cells for ternary ripple-carry addition

IEICE Transactions on Information and Systems, IEICE, 2014

66. High-efficient circuits for ternary addition

VLSI Design, Hindawi, 2014

67. A systematic approach to design Boolean functions using CNFETs and an array of CNFET capacitors

Journal of Circuits, Systems, and Computers, World Scientific, 2014

68. Multi-Vt ternary circuits by carbon nanotube field effect transistor technology for low-voltage and low-power applications

Journal of Computational and Theoretical Nanoscience, ASP, 2014

69. Differential cascode voltage switch (DCVS) strategies by CNTFET technology for standard ternary logic

Microelectronics Journal, Elsevier, 2013

70. CNFET-based design of energy-efficient symmetric three-input XOR and full adder circuits

Arabian Journal for Science and Engineering, Springer, 2013

71. A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

IET Computers & Digital Techniques, IET, 2013

72. Dramatically low-transistor-count high-speed ternary adders

IEEE 43rd International Symposium on Multiple-Valued Logic, 2013

73. Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4≤m≤10) compressors

International Journal of High Performance Systems Architecture, Inderscience, 2013

74. A high-efficient multi-output mixed dynamic/static single-bit adder cell

International Scholarly Research Notices, Hindawi, 2013

75. Design and Implementation of an ASIP-Based Crypto Processor for IDEA and SAFER K-64

International Journal of Design, Analysis and Tools for Integrated Circuits and Systems, 2012

76. An applicable high-efficient CNTFET-based full adder cell for practical environments

The 16th CSI International Symposium on Computer Architecture and Digital Systems, 2012

77. Design and analysis of a high-performance CNFET-based Full Adder

International Journal of Electronics, Taylor and Francis, 2012

78. Design of an ASIP IDEA crypto processor

IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, 2011 

79. A new robust and high-performance hybrid full adder cell

Journal of Circuits, Systems, and Computers, World Scientific, 2011

80. High-speed full adder based on minority function and bridge style for nanoscale

Integration, Elsevier, 2011

81. Efficient CNTFET-based ternary full adder cells for nanoelectronics

Nano-Micro Letters, Springer, 2011

82. Novel direct designs for 3-input XOR function for low-power and high-speed applications

International Journal of Electronics Taylor and Francis, 2010

83. High speed NP-CMOS and multi-output dynamic full adder cells

International Journal of Electrical and Electronics Engineering, 2010

84. New high-performance majority function based full adders

14th International CSI Computer Conference, 2009

85. Design of reliable and high-performance 1-bit full adder cells

14th National CSI Computer Conference, 2009

86. Novel low-power and high-performance full adder cell designs on transistor level

14th National CSI Computer Conference, 2009

87. Two new low-power and high-performance full adders

Journal of Computers, 2009

88. Two new low-power full adders based on majority-not gates

Microelectronics Journal, Elsevier, 2009

89. Ultra high speed full adders

IEICE Electronics Express, IEICE, 2008